Our Team

Prasad - 6+ years in Web3 R&D and protocol design, with deep expertise in decentralized ledger consensus, incentive models, and smart-contract architectures. Bachelor’s in Computer Science & Engineering.

Siva - Academic background in cryptography and blockchain. Computer Engineering degree with strong systems background; Advocates for statistically sound evaluation; has designed and executed large-scale benchmark suites for consensus protocols and cryptographic primitives.

Company Name (if applicable)

Project details

AGI aims to enable systems that can reason, learn and decide in open-ended domains. Today, AGI research is stalled by conventional hardware. GPUs and TPUs excel at dense tensor math but struggle with the irregular, sparse and dynamic workloads at the heart of AGI:

• Recursive reasoning over large knowledge graphs that require pointer chasing, backtracking and dynamic updates.

• Probabilistic inference that demands high-throughput sampling and branching logic.

• Attention and pattern matching that call for real-time selection among high-dimensional vectors.

• Adaptive learning that must update weights or rules on the fly without pausing entire models.

These tasks drive latency into seconds or minutes and energy into hundreds of watts, making real-world deployment impossible. Data movements between memory and CPU add further delay and power drain.

Project Neuromata breaks through these barriers by co-designing hardware and software around AGI’s core primitives. We combine four complementary paradigms—each tailored to specific AGI patterns—to build a brain-inspired accelerator for reasoning, inference and memory tasks:

1. Asynchronous, event-driven neuromorphic cores to handle sparse, dynamic graph processing.

2. Temporal (race logic) modules to solve winner-take-all and shortest-path problems in constant time.

3. Analog in-memory computing arrays for high-throughput vector operations and associative lookups.

4. Processing-in-memory techniques to eliminate data transfer overhead in large knowledge stores.

By integrating these paradigms into a unified architecture, we target order-of-magnitude gains in speed, latency and energy efficiency for AGI applications.

1. Asynchronous Neuromorphic Reasoning

Why it matters
AGI knowledge bases are sparse: only a few concepts activate per query. Conventional hardware must scan entire datasets, wasting power on inactive elements.

Our approach
We model each concept as a spiking neuron. A query triggers spikes in relevant nodes, and only those nodes consume energy. Synaptic weights sit on-chip in small analog or digital memory so activation sums occur locally.

Plan

• Simulation: Build a Python spiking-network simulator for Atomspace graphs, driven by MeTTa queries.

• Prototype: Map the model to an FPGA with asynchronous handshake pipelines or use Intel Loihi boards via research access.

• Metrics: Compare spikes-per-query, energy per spike and query latency versus CPU/GPU baselines. Our target is a 10×–50× energy reduction for graph traversals and sub-second query times on graphs of 10⁵–10⁶ nodes.

This design also supports probabilistic inference through stochastic synapses, embedding randomness in hardware rather than in software.

2. Temporal (Race Logic) Modules

Why it matters
AGI often requires selecting the best among many options (attention, planning). Race logic encodes values as signal delays. The earliest pulse wins, delivering min or argmin in one step.

Our approach

• Implement Delay, Min, Max and Inhibit primitives in simulation or on FPGA delay lines.

• Connect a temporal module to neuromorphic cores: when reasoning paths generate candidate solutions, the race logic picks the fastest (lowest-cost) path. For attention, we convert analog weights to delays and let signals compete.

Plan

• Build an FPGA demo solving a toy planning problem using race logic.

• Measure latency per selection versus iterative digital comparison.

Metrics

• Latency: Aim for sub-microsecond winner selection among hundreds of inputs.

• Energy: Target at least 10× lower energy per operation than digital comparator arrays.

This module accelerates attention mechanisms and graph searches, two major AGI bottlenecks.

3. Analog In-Memory Computing

Why it matters
Linear algebra underpins both deep learning and attention. In analog crossbars, Kirchhoff’s laws sum currents in one physical step, bypassing digital clock cycles.

Our approach

• Use memristor or phase-change memory crossbars to store weight matrices (e.g. transformer key/query).

• Apply voltage vectors as inputs and read summed currents as dot products.

• Compensate for device variability with calibration algorithms to maintain precision within 2%.

Plan

• Simulate an analog crossbar in Python using device-level models.

• If available, run a small analog compute demo on off-the-shelf memristor test hardware or mixed-signal FPGA modules.

• Integrate with MeTTa’s attention routines and benchmark end-to-end performance.

Metrics

• Throughput: Single-cycle analog MAC for entire vectors, offering 50× higher throughput on matrix-vector ops.

• Energy: Achieve tens of TOPS/W for analog inference, well above digital accelerators.

Analog compute collapses the memory wall and supports on-chip learning by updating weights directly in memory elements.

4. Processing-in-Memory (PIM) Techniques

Why it matters
AGI knowledge graphs contain millions of nodes. Transferring data back and forth between DRAM and CPU wastes energy and adds latency.

Our approach

• Explore PIM commands like bulk bitwise operations (AND, OR, XNOR) for fast pattern filtering.

• Prototype a content-addressable memory (CAM) unit for associative lookups, retrieving all rows that match a MeTTa pattern in constant time.

• Use HBM-PIM or simulate DRAM-PIM architectures to evaluate bulk query performance on Atomspace-like datasets.

Plan

• Model a DRAM-PIM with embedded logic in Python and run sample knowledge-graph queries.

• If possible, implement on an FPGA-based DRAM soft-IP with logic extensions.

Metrics

• Latency: 100× faster bulk attribute filtering versus CPU loops.

• Energy: 5×–10× reduction in joules per query.

PIM makes large-scale graph operations feasible in real time and aligns with AGI’s need for rapid, large-data access.

Software-Hardware Co-Design & MeTTa Integration

We will develop a Python-centric co-design framework that unifies algorithm modeling, hardware simulation and benchmarking:

1. Algorithm Modeling: Extend spiking-network and race-logic simulations to accept MeTTa calls.

2. Hardware Simulation: Build lightweight simulators for race logic, analog crossbars and PIM.

3. Benchmark Harness: Feed identical AGI tasks (MeTTa reasoning scripts, attention loops, Bayesian samplers) to simulated hardware and CPU/GPU baselines, measuring latency, energy and accuracy.

This loop lets us refine circuit parameters, test impact on AGI tasks and then map the best designs to hardware prototypes. A MeTTa-to-Neuromata driver will offload supported primitives to hardware or simulation, falling back to CPU for others.

Within SingularityNET’s ecosystem, Neuromata can become the hardware standard for AGI services, unlocking new levels of performance, scalability and deployment flexibility. By co-designing hardware to match AGI’s unique needs, Project Neuromata ensures that future AGI systems can think, learn and adapt as efficiently as biological brains.

Links and references

Pitch Deck - https://drive.google.com/file/d/1tc_xPQ7713ZFS8sZjDBsjxMXbL44cfLW/view?usp=sharing